Sponsored By Introspect Technology Workshop

Testing Parallel Interfaces of the Future: Transmitter and Receiver Test Methods for 28 Gbps and Beyond

Eastern Time September 12, 2019 1:30 pm - 2:00 pm

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Mohamed Hafed

High-speed signaling interfaces are increasingly being used in parallel wireline applications such as processor-to-processor, processor-to-memory, and processor-to-sensor links. These links require very dense — often single-ended — routing while still operating at rates of up to 28 Gbps per pin. This workshop will detail specific test and measurement considerations for ensuring the proper characterization and screening of parallel high-data rate links. We will cover topics such as protocol-based traffic generation and receiver link margining within the context of a parallel system-oriented test methodology.