There are many choices in PCB power integrity design to achieve a specified voltage ripple, or target impedance. For the power net, this includes on which layer(s) to locate it, spacing between the power net and closest ground, and special materials for embedded capacitance. For decoupling, design choices include capacitor location, value(s), interconnect geometry, and total number needed. Typically, PI design is also constrained by high-speed routing considerations to avoid any compromise of routing flexibility. This often prohibits optimizing choices for minimizing inductance in the PI design process. This session begins with a brief overview of the inductance physics and relationship to the current path from the decoupling capacitors to the IC package. Then, it covers the relationship of each inductance piece to the power distribution network impedance. Finally, it presents a systematic approach for determining a layer stackup and a decoupling solution addressing typical design choices.