SI/PI Technical Session

Improve Power Integrity With Decoupling Solutions

Eastern Time October 20, 2020 2:00 pm - 2:30 pm

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James Drewniak

A typical PCB high-speed digital design application can have tens to hundreds of decoupling capacitors for a high-speed power domain, in order to achieve a specified target impedance.  Design choices for applying the decoupling capacitors include where to place them, how to connect them, what values to use, and how many to use.  This presentation will give a brief overview of the inductance contributions of each part of the current path from the decoupling capacitors to the IC package, and how each piece of the inductance is related to the power distribution network impedance.  Then a systematic approach for developing a decoupling solution addressing the typical design choices will be presented.