High-performance I/O interfaces offer small design margin for physical channel impairments such as routing impedance discontinuities and crosstalk. Mitigation techniques commonly deployed in single-purpose test/evaluation boards include thieving pads (copper balance and etch control) and stitching vias (crosstalk reduction and optimal return path). For critical high-speed nets, best practices combine these as “stitched thieving” in a parade-route configuration along the routing net. This approach is not trivial, and it becomes more challenging as designs complexity increases such as in multi-layer PCBs with BGA breakouts. In this workshop, Ted Ballou details strategies for managing layout challenges and addressing practical design constraints. Additionally, he will provide an apples-to-apples comparison of measured results with “before” and “after” PCB design iterations.