The session will include an overview of the Doherty topology and its underlying principles of operation. It will describe the design of a fully integrated Doherty MMIC for the 3.5 GHz frequency band using the 0.4 µm GaN-on-SiC device. Details of the MMIC design, layout and packaging will be described. The measured performance shows good agreement with simulated and clearly demonstrates the advantage of the Doherty architecture.
The packaged MMIC was assembled onto a representative PCB for evaluation and achieved a PSAT of 45 dBm with a peak PAE of 50%. The PAE at 8 dB power back-off was 31.5%. Using a 100 MHz 5G NR signal with 11.5 dB PAPR the EVM was 3.5% and ACLR was less than -33 dBc at 36 dBm (4W) average power.