DDR4 requires tight specifications for high-speed operation, and then to ensure design margins against a target system bit error rate of 1e-16. DDR4 is now able to reach speeds of 3200 Mbps per pin with an FPGA as the memory controller. This talk shows how to model a DDR4 memory channel with an FPGA and demonstrates DDR4 channel and signal integrity analysis for DDR4-3200 speeds. We consider channel characteristics, on-die terminations choices, and equalization controls to optimize our DDR4 signals. The talk includes preliminary analysis that provides channel simulations using Keysight Pathware ADS with the Xilinx Versal FPGA with MICRON memory.