Recently, printed circuit board (PCB) layouts use a double-data rate (DDR) memory. DDR allows two data bit transitions to occur during a single clock cycle, instead of a single data bit transition doubling its data throughput. The increased speed has caused increased complexity of the PCB layout, bus timing, signal integrity and power integrity.
This talk covers factors we must consider including: proper setup/hold time, clean supply voltages, proper termination, trace length matching (including internal length from chip pin until package lead race), topologies for routing VREF, clock and address control, DQS, DQ, power integrity and crosstalk. Samples of DDR4 PCB routing and 6-12 Layers stackup will be demonstrated.