SI/PI Technical Session

A Holistic Power Integrity Approach Reduces Board Spins, Supports System Analysis and Reduces VRM Modeling Effort

Eastern Time October 20, 2020 11:00 am - 11:30 am

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Steven Sandler

I hear many recurring complaints from engineers attending my lectures.  They can be summarized as:

  • Continuously increased technology designs on a constant, short cycle
  • Multilayer board spins are time consuming and expensive. Must be minimized
  • Many key design parameters and guidelines are not provided by the semiconductor manufacturers or are inaccurate.
  • Power electronics engineers rarely get involved in the troubleshooting or modifications caused by their designs. This effort mostly falls on the high-speed engineers.
  • Far too many engineers are developing simulation models for free or inexpensive simulators. This costs valuable engineering time, without creating a net benefit to the system evaluation.

A simple design workflow could address many of these issues, resulting in more cost-effective designs with fewer expensive board spins.

The proposed workflow would also reduce the effort expended by semiconductor companies in developing simulation models.

The result is a unified, end-to-end model, providing power rail noise, spectral content, EMI, dynamic transient response and power rail impedance all within a single model.  This approach also allows the analog, power, digital, RF and uWave models to all be incorporated into a single system level simulation model.