A Holistic Power Integrity Approach Reduces Board Spins, Supports System Analysis and Reduces VRM Modeling Effort

I hear many recurring complaints from engineers attending my lectures.  They can be summarized as: Continuously increased technology designs on a constant, short cycle Multilayer board spins are time consuming and expensive. Must be minimized Many key design parameters and guidelines are not provided by the semiconductor manufacturers or are inaccurate. Power electronics engineers rarely […]

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