A study of risks and factors designers must consider when selecting a resistor component which will be exposed to low duty cycle pulse (LDC) power. Mechanisms and techniques to compare or predict durability of a given selection of thick and thin film components against a projected LDC form is also discussed. In the past 10 […]
Read moreWith the ongoing push to higher-speed and higher-density PCBs designers must improve their understanding of the flow of signals and power throughout the entire board to inform their core responsibilities of developing routing, placement, and layer stack-up strategies. Although your organization may have a dedicated SI/PI team to validate signal integrity and power integrity, SI/PI […]
Read moreMany high-speed digital standards utilise eye analysis on their data stream for verifying signal integrity. This allows engineers to quickly check noise margins and the overall health of their transmitted or received bits. However, most often this implies capturing lots of UIs of the signal and folding each bit to display an eye, which involves […]
Read moreTransmitting data from point A to point B became infinitely more interesting when the Mobile Industry Processor Interface (MIPI) Alliance published the specification for the C-PHY interface. It is faster, lower power, and uses fewer signaling lines than other MIPI interfaces, making it easy to understand why designers of many displays and cameras in mobile […]
Read moreHow can we ensure good Signal Integrity in our designs? The answer lies in matching design practice to data rate. In this talk, Donald Telian presents a data-rate-dependent “cheat sheet” of SI techniques to quickly apply to your design – at any speed. Serial links fail because of discontinuities. But which ones matter? …and why […]
Read moreThe rapidly increasing bandwidth used in the next generation of communication and computational platforms inevitably imposes stringent requirements on the signal integrity and power integrity (SI/PI) of a system. Proper diagnosis of the SI/PI usually requires sophisticated experiments and testing devices. In this workshop we will discuss how performing numerical simulations can improve your work […]
Read moreReduced channel simulation times can be achieved by simulating PCBs and connectors separately then via cascading. However, this approach introduces impedance and crosstalk inaccuracies. This presentation demonstrates the differences through correlated simulation and measurement models. It then uses fields plots to devise mitigation strategies to maintain the increased simulation time while avoiding simulation inaccuracy.
Read moreToday, thousands of engineers are making a career out of managing and improving signal integrity. But 30 years ago, a small, merry band of engineers traveled around Europe and North America in an effort to convince other engineers and managers that in the near future, the integrity of the signal in their designs would be […]
Read moreThe voltage regulator module (VRM) is the foundation of power integrity. Due to their wide bandwidth and low cost, most newer VRM controllers employ transconductance feedback amplifiers, with the VRM manufacturers recommending a shunt compensation for the error amplifier design. However, most VRM designers and power integrity engineers may not be aware that they have […]
Read moreTo meet the next-generation system bandwidth requirement, recently industry and standard bodies are aiming at 800GE and 1.6TE. The next generation switch is targeting 100T capacity as well. The next speed node of 200+ Gbps per lane becomes critical to scale the switch capacity and efficiency of networking bandwidth. In this talk Cathy will discuss […]
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