System Oriented Testing for Memory Interfaces

Next-generation data center and server architectures rely heavily on high-speed signaling interfaces. No longer restricted to the networking sub-systems of the data center, these high-speed interfaces are used to connect processors, AI hardware accelerators, switching and routing fabrics, and of course extremely high-density memory channels. Testing these highly parallel signaling interfaces represents a particular challenge […]

Read more

Update Your SI / PI Design and Analysis Methodology for DDR and GDDR Memory Interfaces

Memory interfaces continue to be the biggest challenge for signal and power integrity teams.  Simultaneous switching of single-ended signals at the speeds of serial links take this design challenge to a new level over the well-behaved differential pairs of peripheral component interconnect express (PCI Express).  With voltage swings below one volt for the low-power versions […]

Read more

Using TDR to Solve Signal Integrity Issues

Gone are the days where only basic voltage and timing measurements would suffice for validating a high-speed design. Large-scale design integration with devices such as SoCs or FPGA require strict impedance control, tight timing references and a host of other complex parameters to manage. How do you efficiently address signal integrity issues? Where do you […]

Read more

PAM-Fried Engineer’s Guide to Crosstalk, ISI, FEC, Equalization

In this talk, we’ll see how crosstalk, ISI (inter-symbol interference), FEC (forward error correction), and equalization have driven high speed IO away from NRZ (which should be PAM2–2-level pulse amplitude modulation) to the madness of PAM4, PAM5, PAM6, PAM-fried engineers. Along the way, we’ll investigate how simple, righteous design constraints have evolved to arbitrarily complicated […]

Read more

Real World 112 Gbps PAM4 System Architectures

As 112 Gbps PAM4 data rates become reality, developers are challenged with balancing increasing throughput, scalability and density demands with concerns such as power consumption, signal integrity, cost and time-to-market. In this keynote, Samtec will demonstrate real-world solutions from front-panel to mid-board, mid-board to backplane, high-performance test and on-package system architectures that exceed the demands […]

Read more

Bending Electromagnetic Simulation Tools to Your Will – How to Design 112 Gbps Systems Every Time

There is an art and science to utilizing an electromagnetic modeling tool to analyze and optimize designs and obtain reasonable answers consistently.  Session attendees will learn how to “trick” a tool into providing the most accurate insight possible for a design.  We’ll talk about setup, ports, boundary conditions and other tricks of the trade that […]

Read more

Circuit Modeling for High-Speed Communication in 5G, IoT, and SatCom Applications

The performance of microwave and millimeter-wave antennas and circuits plays a key role in the application area of 5G, the internet of things (IoT), and satellite communication.  The evaluation of such devices before fabrication and testing through electromagnetics simulation tools is beneficial to reduce the time and effort required in the design process during the […]

Read more

My Simulator Is a Soldering Iron: PDN Design Guidelines With an Homage to Bob Pease

We will explore the four most important design guidelines for the power distribution network using a simple prototype circuit in which we can actually measure the noise on the PDN, while we make interconnect changes and component changes. While we do not recommend designing your product by building it and testing, we can gain some […]

Read more

Improve Power Integrity With Decoupling Solutions

A typical PCB high-speed digital design application can have tens to hundreds of decoupling capacitors for a high-speed power domain, in order to achieve a specified target impedance.  Design choices for applying the decoupling capacitors include where to place them, how to connect them, what values to use, and how many to use.  This presentation […]

Read more

DDR4-3200 Channel Modeling and Signal Integrity Analysis Using an FPGA

DDR4 requires tight specifications for high-speed operation, and then to ensure design margins against a target system bit error rate of 1e-16. DDR4 is now able to reach speeds of 3200 Mbps per pin with an FPGA as the memory controller. This talk shows how to model a DDR4 memory channel with an FPGA and […]

Read more